1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of transistor channel length.
2. Description of the Relevant Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline silicon ("polysilicon") material over a relatively thin gate oxide arranged above a semiconductor substrate. The polysilicon material and the gate oxide are patterned to form a gate conductor with source/drain regions (i.e., junctions) adjacent to and on opposite sides of the gate conductor within the substrate. The gate conductor and source/drain regions are then implanted with an impurity dopant. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET ("n-channel") transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET ("p-channel") transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single monolithic substrate.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to reduce the transistor threshold voltage, V.sub.T. Several factors contribute to V.sub.T, one of which is the effective channel length ("Leff") of the transistor. The distance between the source-side junction and the drain-side junction of a transistor is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the junctions, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length. In VLSI designs, as the physical channel length is decreased, the Leff is also decreased. As Leff becomes smaller, the distance between the depletion regions associated with the source and drain areas within the junctions of a transistor decreases. As a result, less gate charge is required to invert the channel of a transistor having a short Leff. Accordingly, reducing the physical channel length, and hence the Leff, can lead to a reduction in the threshold voltage of a transistor. Consequently, the switching speed of the logic gates of an integrated circuit employing transistors with reduced Leff is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies).
Unfortunately, minimizing the physical channel length of a transistor is somewhat limited by conventional techniques used to define the gate conductor of the transistor. As mentioned earlier, the gate conductor is typically formed from a polysilicon material. A technique known as "lithography" is used to pattern a photosensitive film (i.e., "photoresist") above the polysilicon material. An optical image is transferred to the photoresist by projecting a form of radiation, primarily ultraviolet light, through the transparent portions of a mask plate. The solubility of regions of the photoresist exposed to the radiation is altered by a photochemical reaction. The photoresist is then washed with a solvent that preferentially removes resist areas of higher solubility. As such, the now patterned photoresist exposes portions of the polysilicon material to be removed and covers the portion of the polysilicon material to be retained for the gate conductor. Those exposed portions of the polysilicon material not protected by photoresist are then etched. The photoresist, being substantially resistant to attack by etchants, remains intact during the etch step, and thereby prevents underlying material from being etched. In this manner, opposed sidewall surfaces for the polysilicon material arranged underneath the photoresist are defined to form a gate conductor.
The lateral width (i.e., the distance between opposed sidewall surfaces) of a gate conductor as defined by the lateral width of an overlying photoresist layer dictates the physical channel length of a transistor. Unfortunately, the minimum lateral dimension that can be achieved for a patterned photoresist layer is limited by, inter alia, the resolution of the optical system (i.e., aligner or printer) used to project an image onto the photoresist. The term "resolution" describes the ability of an optical system to distinguish closely spaced objects. The resolution of modern aligners is mainly dependent upon diffraction effects in which radiation passing past an edge or through a slit on a masking plate spreads into regions not directly exposed to oncoming waves. As such, the features patterned upon a masking plate may not be correctly printed onto photoresist. Particularly, the images projected onto photoresist typically have larger dimensions than intended.
It would therefore be desirable to develop a transistor fabrication technique in which the channel length of the transistor is reduced so as to provide for high frequency operation of an integrated circuit employing the transistor. More specifically, a process is needed in which the resolution of an optical aligner no longer limits the minimum achievable dimensions of a patterned photoresist feature. Once the dimensions of a photoresist feature are minimized, the lateral width of a gate conductor patterned using optical lithography can be reduced. Since the lateral width of a gate conductor dictates the physical channel length of a transistor, such a process would cause a reduction in the Leff of a transistor as well. Minimizing Leff could have the advantageous effect of lowering the threshold voltage of the transistor.